Though various types of floating gate non-volatile memory devices exist, many require obtaining a thin tunnel oxide layer on a semiconductor substrate, mostly commonly a silicon substrate. For example, Hurley (U.S. Patent Publication No. 2003/0011018) describes a method in which openings are made in a tunnel oxide layer and monocrystalline silicon is epitaxially grown over the tunnel oxide with the openings serving as seed areas for the epi-growth. This is an example of so-called selective epitaxial growth of silicon during which the nucleation of polycrystalline silicon on top of, for example, silicon nitride/oxide layers is prevented. The monocrystalline material will form the actual floating gate in the finished device.
In selective epitaxial growth, it is important to clean the seed areas and to remove the native oxide before the epi-growth begins. This conventional cleaning process usually comprises a wet chemical clean having a last step treatment with aqueous solutions containing hydrogen fluoride, a so-called ‘HF dip’. However, this step may cause uncontrolled thinning of the tunnel oxide, which may lead to reproducibility issues, and possibly the appearance of areas of non-uniform tunnel oxide thickness.
In some flash memory devices, arrays of columnar floating gate structures are produced from polysilicon to have a certain thickness between parallel sidewalls. An oxide-nitride-oxide (ONO) inter-poly dielectric runs along the sidewalls of the floating gate in order to provide a large capacitance between floating gate and control gate and therefore a large coupling ratio.
In order to scale the cell, it is necessary to reduce one or more of the length of the floating gate, the length of the control gate, and the thickness of the inter-poly dielectric. For scaled devices, the length of the structures are becoming smaller and the patterns denser. The limit of scaling would be given by a half-pitch filled by the inter-poly dielectric (on both sides). This implies that the pitch of floating gates (defined as the sum of the floating gate length and the space between two adjacent floating gates) cannot be scaled below a value which corresponds to the sum of the floating gate length (scalable to about 5 nm), the control gate length (scalable to about 5 nm), and two times the ONO inter-poly thickness (scalable to about 15 nm). This gives a total sum of about 40 nm and therefore a limit of scaling of 20 nm half-pitch, meaning a half-pitch below 20 nm is difficult to achieve. While this value could be reduced by making a thinner vertical inter-poly dielectric, but this is not trivial for the ONO stacks typically in use.
Floating gate memory devices may be operated array in a manner similar to NAND memories, as described, for example, in “Nonvolatile Memory Technologies with Emphasis on Flash: a Comprehensive Guide to Understanding and Using NVM Devices,” IEEE Press Series on Microelectronic Systems, pp. 227-237 (J. Brewer and M. Gill, eds., 2007).